The present invention relates to a memory device and a method of repairing the same. More particularly, the present invention relates to a memory device and a method of repairing the same which performs repair of at least one memory cell using a latch circuit and a register.
Generally, a NAND flash memory device adds a redundancy cell to a main memory cell to enhance the yield thereof. Accordingly, when at least one failure occurs to a certain memory cell, the NAND flash memory device employs a repairing method of substituting the redundancy cell for the failed memory cell.
When an address signal is inputted to the redundancy cell in the memory device, a redundancy detecting circuit detects the address signal and outputs a repair controlling signal including repair information. In addition, the redundancy detecting circuit stores repair address information programmed by a fuse device.
The failed memory cell is substituted with a redundancy memory cell, i.e. is repaired in accordance with the repair controlling signal.
FIG. 1 is a view illustrating a redundancy circuit for repairing a common memory device in accordance with conventional methods.
Referring to FIG. 1, the redundancy circuit includes a guard fuse block 110 and an address fuse block 120.
The guard fuse block 110 includes a guard fuse (hereinafter, referred to as “GF”), a first to third invertors IN1 to IN3, and a first and second N-MOS transistors N1 and N2.
The address fuse block 120 has a first P-MOS transistor PI, a third to eleventh N-MOS transistors N3 to N11, a fourth and fifth inverters IN4 and IN5, and a first to eighth address fuses (hereinafter, referred to as “AF”) AF1 to AF8.
Address signals RLA<0:3> and RLAb<0:3> are inputted to the third to tenth N-MOS transistors included in the address fuse block 120. The third to tenth N-MOS transistors store a repair address signal according as the guard fuse GF depending on a repair address and a first, fourth, fifth and eighth address fuses AF1,AF4,AF5 and AF8 are cut.
When a power source is inputted to the redundancy circuit, current flows from a node C in the direction of an arrow P. A repair signal REPb having low logic (e.g., 0 V) is outputted by the current flowing from the node C, and a repair address signal is outputted in accordance with an inputted address.
When employing the redundancy circuit for column repair of the memory device, many fuse devices are required.
That is, the smaller the memory device is, the more repair fuses are required. In addition, since the fuse circuit for repairing detects the comparison of a column address through current sensing, the consumption of current in the memory device can become undesirably high. Furthermore, when a fuse is cut it is difficult to reuse the fuse.